Publications
2017
Journal Articles
· A. Aziz, N. Shukla, S. Datta and S. K. Gupta, “Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective-Part I”, IEEE Transactions on Electron Devices.
· A. Aziz, N. Shukla, S. Datta and S. K. Gupta, “Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective-Part II”, IEEE Transactions on Electron Devices.
Conference Proceedings
· S. K. Gupta, D. Wang, S. George, A. Aziz, X. Li, S. Datta and V. Narayanan, “Harnessing Ferroelectrics for Non-volatile Memories and Logic”, to appear in International Symposium on Quality Electronic Design, 2017. (Invited)
Book Chapters
· X. Li, M. S. Kim, S. George, A. Aziz, M. Jerry, N. Shukla, J. Sampson, S. K. Gupta, S. Datta, and V. Narayanan, “Emerging Steep-Slope Devices and Circuits: Opportunities and Challenges”, Submitted for possible publication in Beyond CMOS, 2017, Springer.
2016
Journal Articles
· A. Aziz, N. Jao, S. Datta and S. K. Gupta, “Analysis of Functional Oxide Based Selectors for Cross-Point Memories”, IEEE Transactions on Circuits & Systems-I: Regular Papers.
· A. Aziz and S. K. Gupta, “Hybrid Multiplexing (HYM) for Read- and Area-Optimized MRAMs with Separate Read-Write Paths,” IEEE Transactions on Nanotechnology.
· A. Aziz, S. Ghosh, S. Datta and S. K. Gupta, “Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors”, IEEE Electron Device Letters.
· S. Srinivasa, A. Aziz, N. Shukla, X. Li, J. Sampson, S. Datta, J. P. Kulkarni, V. Narayanan and S. K. Gupta, “Correlated Material Enhanced SRAMs with Robust Low Power Operation”, IEEE Transactions on Electron Devices.
· M. S. Kim, W C- Wissing, X. Li, J. Sampson, S. Datta,S. K. Gupta and V. Narayanan, “Comparative Area and Parasitics Analysis in FinFET and Hetero-junction Vertical TFET Standard Cells”, ACM Journal of Emerging Technologies in Computing.
Conference Proceedings
· N. Shukla, B. Grisafe, R. K. Ghosh, N. Jao, A. Aziz, J. Froujier, M. Jerry, S. Sonde, S. Rouvimov, T. Orlova, S. Guha, S. K. Gupta, and S. Datta, “Ag/HfO2 based Threshold Switch with Extreme Non-Linearity for Unipolar Cross-Point Memory and Steep-slope Phase-FETs”, International Electron Device Meetings (IEDM), 2016.
· A. Aziz, S. Ghosh, S. K. Gupta, and S. Datta, “Polarization Charge and Coercive Field Dependent Performance of Negative Capacitance FETs”, Device Research Conference (DRC) 2016.
· X. Yin, A. Aziz, J. Nahas, S. Datta, S. K. Gupta, M. Nimier and X. S. Hu, “Exploiting Ferroelectric FETs for Low-Power Non-Volatile Logic-in-Memory Circuits”, International Conference On Computer Aided Design, 2016.
· S. George, A. Aziz, X. Li, M. S. Kim, J. Sampson, S. Datta, S. K. Gupta, V. Narayanan, “Device –Circuit Co Design of FEFET Based Logic for Low Voltage Processors”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2016.
· S. George, K. Ma, A. Aziz, X. Li, J. Sampson, A. Khan, S. Salahuddin, M.-F. Chang, S. Datta, S. K. Gupta, and V. Narayanan, “Nonvolatile Memory Design Based on Ferroelectric FETs”, Design Automation Conference (DAC) 2016.
· J. Frougier, N. Shukla, D. Deng, M. Jerry, A. Aziz, L. Liu, G. Lavallee, T. S. Mayer, S. K. Gupta and S. Datta,“Phase-transition-FET Exhibiting Steep Switching Slope of 8mV/decade and 36% Enhanced ON Current”, IEEE Symposium on VLSI Technology, 2016.
· S. K. Gupta, A. Aziz, N. Shukla and S. Datta, “On the Potential of Correlated Materials in the Design of Spin-Based Cross-Point Memories”, International Symposium on Circuits and Systems (ISCAS)2016 (Invited).
Book Chapters
· S. K. Gupta and K. Roy, “Low Power Robust FinFET based SRAM Design in Scaled Technologies” Circuit Design for Reliability, 2015 (Ed. R. Reis, Yu Cao and G. Wirth), Springer New York.
2015
Journal Articles
· N. Shukla, A. V. Thathachary, A. Agrawal, H. Paik, A. Aziz, D. G. Schlom, S. K. Gupta, R. E.Herbert, and S. Datta, “A steep slope transistor based on abrupt electronic phase transition”, Nature Communications, August 2015.
Conference Proceedings
· A. Aziz, N. Shukla, S. Datta and S. K Gupta, “Implication of Hysteretic Selector Device on the Biasing Scheme of a Cross-point Memory Array”,International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015.
· A. Aziz, N. Shukla, S. Datta and S. K Gupta, “COAST: Correlated Material Assisted STT MRAMs for Optimized Read Operation“, International Symposium on Low Power Electronics and Design (ISLPED),2015.
· A. Aziz, N. Shukla, S. Datta and S. K Gupta, “Read Optimized MRAM with Separate Read-Write Paths based on Concerted Operation of Magnetic Tunnel Junction with Correlated Material“, Device Research Conference,2015.
· A. Aziz, W. Cane-Wissing, M. S. Kim, S. Datta, V. Narayanan and S. K. Gupta, “Single-Ended and Differential MRAMs based on Spin Hall Effect: A Layout-Aware Design Perspective“ ISVLSI,2015 (Invited).
· M. S. Kim, W. Cane-Wissing, J. Sampson, S. Datta, V. Narayanan and S. K. Gupta, “Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs“ ISVLSI,2015.
· K. Ma, N. Chandramoorthy, X. Li, S. K. Gupta, J. Sampson, Y. Xie, V. Narayanan, “Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing”, ISVLSI, 2015.
· Xueqing Li, Unsuk Heo, Huichu Liu, S. K. Gupta, Suman Datta and Vijaykrishnan Narayanan, “A High-Efficiency Switched-Capacitance HTFET Charge Pump For Low-Input-Voltage Applications”, International Conference on VLSI Design, 2015.
Book Chapters
· S. K. Gupta and K. Roy, “Low Power Robust FinFET based SRAM Design in Scaled Technologies” Circuit Design for Reliability, 2015 (Ed. R. Reis, Yu Cao and G. Wirth), Springer New York.
2014
Journal Articles
· W. S. Cho, S. K. Gupta and K. Roy, “Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10nm Technologies”, to appear in IEEE Transactions on Electron Devices.
· S. H. Choday, S. K. Gupta and K. Roy, “Write-Optimized STT-MRAM Bit-cells Using Asymmetrically Doped Transistors”, IEEE Electron Device Letters, vol. 35, no. 11, Nov 2014.
Conference Proceedings
· S. Datta, R. Pandey, A. Agrawal, S. K. Gupta and R. Arghavani, “Impact of Contact and Local Interconnect Scaling on Logic Performance,” VLSI Tech. Symp. 2014. (Invited)
· K. Ma, H. Lu, Y. Xiao, Y, Zheng, X. Li, S. K. Gupta, Y. Xie and V. Narayanan, “Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed”, “ ISVLSI, 2014.
Invited Talks
· S. K. Gupta, "Low Power Robust Design of FinFET-based Circuits using a Technology-Circuit Co-optimization Approach”, 9th International Front-End Electronics (FEE) Conference, 2014.
2013
Journal Articles
· S. K. Gupta and K. Roy, “Device-Circuit Co-optimization for Robust Design of FinFET-based SRAMs ”, IEEE Design & Test of Computers, vol. 30, no. 6, pp. 29-39, Dec. 2013 (Invited).
· S. K. Gupta, J. P Kulkarni and K. Roy, “Tri-Mode Independent Gate FinFET with Pass-Gate Feedback: A Device-Circuit Co-design Approach for Enhanced Cell Stability”, IEEE Transactions on Electron Devices, vol. 60, no. 11, Nov. 2013, pp: 3696-3704.
· N. N. Mojumder, X. Fong, C. Augustine, S. K. Gupta, S. H. Choday and K. Roy, “Spin-Transfer Torque MRAMs for Low Power Applications”, ACM Journal of Emerging Technologies in Computing, vol. 9, no. 2, 2013.
Conference Proceedings
· S. K. Gupta, W. Cho, A, Goud, K, Yogendra and K. Roy, “Design Space Exploration of FinFETs in sub-10nm Technologies for Energy-Efficient Near-Threshold Circuits”, Device Research Conference, 2013.
· A. Goud, S. K. Gupta, S. H. Choday and K. Roy, “Atomistic Tight-Binding based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5 nm Gate Length Si FinFETs“, Device Research Conference, 2013.
2012
Journal Articles
· S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, “Heterojunction Intra-band Tunneling (HIBT) FETs for Low Voltage SRAMs”, IEEE Transactions on Electron Devices, vol. 59, no.12, pp: 3533-3542, December 2012.
· S. K. Gupta, G. Panagopoulos and K. Roy, “NBTI in n-type SOI access FinFETs in 6T SRAM and its impact on cell stability and performance", IEEE Transactions on Electron Devices, vol. 59, no. 10, pp: 2603-2609, October 2012.
· M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui and K. Roy, " Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT", ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no. 2, June 2012.
Conference Proceedings
· S. K. Gupta and K. Roy, “Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-design Approach”, Electro Chemical Society Symposium 2012 (Invited) (Rated amongst the top 8 papers in the entire conference).
· S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, “Dopant Straggle-Free Heterojunction Intra-band Tunneling (HIBT) FETs with Low Drain-induced Barrier Lowering/Thinning and Reduced Variation in OFF current”, Device Research Conference, pp: 55-56, 2012.
· D. Lee, S. K. Gupta and K. Roy “High-Performance Low-Energy STT MRAM Based on Balanced Write Scheme”, International Symposium on Low Power Electronics and Design (ISLPED), pp : 9-14, 2012.
· Y. Kim, S. K. Gupta, S. P. Park, G. Panagopoulos and K. Roy “Write-Optimized Reliable Design of STT MRAM” International Symposium on Low Power Electronics and Design (ISLPED), pp : 3-8, 2012. (Nominated for Best Paper Award).
· S. P. Park, S. K. Gupta, N. N. Mojumder, A. Raghunathan and K. Roy, “ Future Cache Design using STT MRAMs for Improved Energy Efficiency: Devices, Circuits and Architecture”, Design Automation Conference, pp: 492-497, 2012.
· S. K. Gupta, S. P. Park, N. N. Mojumder and K. Roy, “Layout-Aware Optimization of STT MRAMs”, Design Automation and Test in Europe Conference, pp: 1455-1458, 2012.
2011
Journal Articles
· F. Moradi, S. K. Gupta, G. Panagopoulos, H. Mahmoodi, D. T. Wisland and K. Roy, “Asymmetrically-doped (AD) FinFET for Low Power Robust SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 12, pp: 4241-4249, December 2011.
· S. K. Gupta, S. P. Park and K. Roy, “Tri-mode Independent Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 11, pp: 3837-3846, November 2011.
· S. Raghunathan, S. K. Gupta, H. Markandeya, P.P. Irazoqui and K. Roy, “Ultra-Low-Power Algorithm design for Implantable Devices- Application to Epilepsy Prostheses”, Journal of Low Power Electronics and Applications, vol. 1, no. 1, pp: 175-203, May 2011 (Invited).
· N. N. Mojumder, S. K. Gupta, S. H. Choday, D. E. Nikonov and K. Roy, “Three-Terminal Dual-Pillar STT-MRAM Device for High-Performance Robust Memory Applications," IEEE Tranactions on Electron Devices, vol. 58, no. 5, pp: 1508-1516, May 2011.
· A. Goel, S. K. Gupta and K. Roy, “Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low Power and Robust SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 2, pp: 296-308, Feb 2011.
Conference Proceedings
· S. K. Gupta, S. H. Choday and K. Roy, “Exploration of Device-Circuit Interactions in FinFET-based Memories for sub-15nm Technologies using a Mixed Mode Quantum Simulation Framework: Atoms to Systems”, International Electron Device Meetings, pp: 32.5.1-32.5.4, 2011.
· X. Fong, S. K. Gupta, N. N. Mojumder, H. Choday, C. Augustine, and Kaushik Roy, “KNACK: A Hybrid Spin-Charge Mixed-Mode Simulator for Evaluating Different Genres of Spin-Transfer Torque MRAM Bit-cells”, International Conference on Simulation of Semiconductor Processes and Devices, pp: 51-54, 2011.
· N. N. Mojumder, S. K. Gupta and K. Roy, “Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations”, Device Research Conference, pp: 67-68, 2011.
· S. Dighe, S. K. Gupta, V. De, S. Vangal, N. Borkar, S. Borkar and K. Roy, “A 45nm 48-core IA processor with Variation-Aware Scheduling and Optimal Core Mapping” IEEE VLSI Circuit Symposium, pp: 250-251, 2011.
· M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui, K. Roy, " Ultra Low Power, LPF-Only DWT Architecture for an Epileptic Seizure Prosthesis Implant", Subthreshold Microelectronics Conference, 2011.
2010
Journal Articles
· S. Raghunathan, S. K. Gupta, H. Markandeya, K. Roy and P. P. Irazoqui, “A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications”, Journal of Neuroscience Methods, vol 193, no. 1, pp: 106-117, Oct. 2010.
· S. K. Gupta, A. Raychowdhury and K. Roy, "Digital computation in sub-threshold regime for ultra-low power operation: A device-circuit-system co-design perspective”, Proceedings of the IEEE, vol. 98, no. 2, pp: 160-190, Feb 2010 (Invited)
2009
Journal Articles
· S. Raghunathan, S. K. Gupta, M. P. Ward, R. M Worth, K. Roy and P. Irazoqui, “The design and hardware implementation of a low-power real-time seizure detection algorithm”, Journal of Neural Engineering, vol. 6, 056005, Oct. 2009.
· S. K. Gupta, A. Raychowdhury and K. Roy, “Compact models considering incomplete voltage swing in CMOS circuits at ultra-low voltages: A circuit perspective on limits of switching energy”, Journal of Applied Physics, vol. 105, no. 9, 094901, May 2009.
Conference Proceedings
· K. Roy, J. P. Kulkarni and S. K. Gupta, “Device/Circuit Interactions at 22nm Technology Node”, Design Automation Conference, pp: 97-102, 2009 (Invited).
· A. Goel, S. K. Gupta, A. Bansal, M.-H. Chiang and Kaushik Roy, “Double-Gate MOSFETs with Asymmetric Drain Underlap: A device-circuit co-design and optimization perspective for SRAM”, Device Research Conference, pp: 57-58, 2009.
· S. Raghunathan, S. K. Gupta, H. Markandeya, K. Roy and P. Irazoqui, “Co-design of hardware and software to optimize seizure prediction and detection algorithms towards a closed loop epilepsy prosthesis”, Proceedings of the American Epilepsy Society (AES) Annual Meeting, 2009.
· S. Raghunathan, S. K. Gupta, K. Roy and P. Irazoqui, “An implantable ultra-low power digital circuit implementation of a seizure detection algorithm”, BMES Annual Fall Meeting, 2009.
2008 & before
Journal Articles
· M. J. Kumar, V. Venkataraman and S. K. Gupta, "A New Grounded Lamination Gate (GLG) for Diminished Fringe Capacitance Effects in High-K Gate Dielectric MOSFETs", IEEE Transactions on Electron Devices, vol. 53, no. 10, pp: 2578-2581, October 2006.
· M. J. Kumar, S. K. Gupta and V. Venkataraman, “Compact Modeling of the Effects of Parasitic Internal Fringe Capacitance on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 53, no. 4, pp: 706-711, April 2006.
· V. Venkataraman, S. K. Gupta and M. J. Kumar, "On the Parasitic Gate Capacitance of Small Geometry MOSFETs," IEEE Transactions on Electron Devices, vol. 52, no. 7, pp: 1676-1677, July 2005.
Conference Proceedings
· M. J. Kumar, V. Venkataraman and S. K. Gupta, "A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects," Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, pp. 709-712, 2006.
· M. J. Kumar, V. Venkataraman and S. K. Gupta, "Compact Modeling of Parasitic Internal Fringe Capacitance and its effect on the Threshold Voltage of High-K Gate Dielectric SOI MOSFETs", Int. Workshop on the Physics of Semiconductor Devices, 2005.
Book Chapters
· V. Venkataraman, S. K. Gupta and M. J. Kumar, "Laser Processing of Materials in Nanotechnology," Encyclopedia of Nanoscience and Nanotechnology, 2nd Edition, 2008, (Ed. H.S.Nalwa), American Scientific Publishers, CA, USA.
PATENTS
· S. K. Gupta, A. Aziz, N, Shukla, S. Datta, X. Li and V. Narayanan, "Correlated Material Enhanced Memories and Peripheral Circuits for Non-Volatile Storage” Application filed. (Application No: 62/346,207).
· S. Raghunathan, S. K. Gupta, P. Irazoqui and K. Roy, "A Nano-power Real-time Seizure Detection System on Chip” Application filed. (Application No: 12/144.452)
· M. J. Kumar, S. K. Gupta and V. Venkataraman, "A new grounded lamination gate structure for controlling parasitic fringe capacitance effects in MOSFETs,” Application filed. (Application No: 1693/DEL/2006 dated 24-07-2006).